package moore.generator.template

class PipoTemplateClass {
	def	public static String getPipo(){
		'''
		library IEEE;
		use IEEE.STD_LOGIC_1164.ALL;
		
		-- Uncomment the following library declaration if using
		-- arithmetic functions with Signed or Unsigned values
		--use IEEE.NUMERIC_STD.ALL;
		
		-- Uncomment the following library declaration if instantiating
		-- any Xilinx primitives in this code.
		library UNISIM;
		use UNISIM.VComponents.all;
		
		entity PIPO is
		GENERIC(
			dim: integer:= 4
		);
		PORT(
			data_in: in std_logic_vector( dim-1 downto 0);
			data_out: out std_logic_vector(dim-1 downto 0);
			CE: in std_logic;
			Clk: in std_logic;
			Reset: in std_logic
		);
		end PIPO;
		
		architecture Structural of PIPO is
		
		begin
		-- genero tutte le connessioni interne
			REG_GEN:for I in 0 to dim-1 generate
		      FDCE_inst : FDCE
								generic map (
									INIT => '0') -- Initial value of register ('0' or '1')  
								port map (
									Q => data_out(I),      -- Data output
									C => Clk,      -- Clock input
									CE => CE,    -- Clock enable input
									CLR => Reset,  -- Asynchronous clear input
									D => data_in(I)       -- Data input
								);
		   end generate REG_GEN;
		
		end Structural;
		'''
	}
}